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Altera_Forum
Honored Contributor
Honored Contributorddr3 sdram controller (UniPHY) afi_half_clk doesn't work but status signals work fine
I have build a qsys system, that niosII connects a mm bridge then connects with ddr3 controller. I use afi_clk to drive the nios II. And then I export the afi_half_clk to external qsys to drive a cou...
Altera_ForumHonored Contributor
Honored ContributorAs I recall, there was a defect in an earlier quartus release where the afi_half_clk was left disconnected inside the UNIPHY IP even if one selected the "enable afi half clock" check box. I have recently observed that the UNIPHY afi half clock was working correctly in quartus 13.1. IMHO, perhaps Altera could improve quality control if it was easier for customers to select the IP release independently of the quartus release.
