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Altera_Forum's avatar
Altera_Forum
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11 years ago

ddr3 sdram controller (UniPHY) afi_half_clk doesn't work but status signals work fine

I have build a qsys system, that niosII connects a mm bridge then connects with ddr3 controller. I use afi_clk to drive the nios II. And then I export the afi_half_clk to external qsys to drive a cou...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Yes, via the "enable half rate clock" check box. I also enable the half rate configuration for the DDR2 controller.

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You are correct. After I tick the check box and regenerate the files, then the half rate clock toggle in my design properly. Thanks very much.