ddr3 sdram controller (UniPHY) afi_half_clk doesn't work but status signals work fine

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As I recall, there was a defect in an earlier quartus release where the afi_half_clk was left disconnected inside the UNIPHY IP even if one selected the "enable afi half clock" check box. I have recently observed that the UNIPHY afi half clock was working correctly in quartus 13.1. IMHO, perhaps Altera could improve quality control if it was easier for customers to select the IP release independently of the quartus release.

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Thanks for reply. However, what I use is Quartus 13.1. And it seems there is no option in DDR UNIPHY IP to configure enable or disable "afi half clock". In your design, do you configure it to enable the half clock?

Thanks.