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Altera_Forum
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11 years ago

Custom ip: can't see IRQ number in system.h

Hello,

I'm trying to create a custom component which should generate an interrupt to the NIOS.

My problem is that the BSP generate the system.h with no interruption for the component.

Qsys plugged it to input 4, but BSP irq value is -1 as well as irq_interrrupt_controller_id

I tried to follow several document from Altera literature but no success.

The component has an Avalon MMSlave, a clock input, a reset input, an Interrupt Sender and several Conduit.

in the _sw.tcl there is the isr_preemption_supported set to true and supported_interrupt_apis to "legacy_interrupt_api enhanced_interrupt_api".

The driver code contains only the _regs.h file

The vhdl skeleton of the device is created but not the full behaviour, I don't think that BSP generation check this level of detail.

Can anyone help me with this issue?

Thanks

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Also,

    As the guys above stated make sure your _hw.tcl file is correct. It is located in your root quartus project directory labeled projectname_hw.tcl. I've attached mine to this post so you can check it out. If you are getting the same warning mentioned above you may want to modify the "associatedaddressablepoint" with the name of you IRQ_RECIEVER in your Qsys custom component. I think you have to be careful to to make sure it is the name of the irq block in your interfaces tab and NOT the name of you Avalon Memory Mapped Slave which is probably s0. You can see in my that my irq sender is irq_s0.

    Side note: For some reason Qsys doesn't pick up changes made to custom components very well. You may have to add/remove the component a couple times before Qsys picks up the change. This is very aggravating especially if you don't realize your changes are not getting updated when you re-add the component you made changes to.

    Hope this info helps.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I only skimmed through the post so maybe I missed this but did you make sure the interrupt sender from your slave port is connected to the Nios II interrupt receiver? If not that will cause it to show up as a -1 in system.h

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I have run into the same problem with my project in Quartus 13.1. I have two instances of a custom component in my design, and the interrupts are set to -1 in the system.h file. When I first checked the _hw.tcl file, the associatedAddressablePoint was blank. I had used the default "interrupt_sender" name in the component, so I renamed it. After I regenerated the component with this change, the associatedAddressablePoint was set as follows:

    # # connection point AD9637_irq_sender#

    add_interface AD9637_irq_sender interrupt end

    set_interface_property AD9637_irq_sender associatedAddressablePoint AD9637_irq_sender

    set_interface_property AD9637_irq_sender associatedClock adc_clk

    set_interface_property AD9637_irq_sender associatedReset reset

    set_interface_property AD9637_irq_sender ENABLED true

    set_interface_property AD9637_irq_sender EXPORT_OF ""

    set_interface_property AD9637_irq_sender PORT_NAME_MAP ""

    set_interface_property AD9637_irq_sender CMSIS_SVD_VARIABLES ""

    set_interface_property AD9637_irq_sender SVD_ADDRESS_GROUP ""

    add_interface_port AD9637_irq_sender ad9637_irq irq Output 1

    I then fully replaced the components in qsys and verified that the interrupt sender name changed on the component. I assigned the IRQ in qsys and re-generated the design and the BSP for the Nios. However, I still do not see the interrupt in system.h:

    /*

    * AD9637_interface_0 configuration

    *

    */

    # define AD9637_INTERFACE_0_BASE 0x1000# define AD9637_INTERFACE_0_IRQ -1# define AD9637_INTERFACE_0_IRQ_INTERRUPT_CONTROLLER_ID -1# define AD9637_INTERFACE_0_NAME "/dev/AD9637_interface_0"# define AD9637_INTERFACE_0_SPAN 1024# define AD9637_INTERFACE_0_TYPE "AD9637_interface"# define ALT_MODULE_CLASS_AD9637_interface_0 AD9637_interface

    /*

    * AD9637_interface_1 configuration

    *

    */

    # define AD9637_INTERFACE_1_BASE 0x1400# define AD9637_INTERFACE_1_IRQ -1# define AD9637_INTERFACE_1_IRQ_INTERRUPT_CONTROLLER_ID -1# define AD9637_INTERFACE_1_NAME "/dev/AD9637_interface_1"# define AD9637_INTERFACE_1_SPAN 1024# define AD9637_INTERFACE_1_TYPE "AD9637_interface"# define ALT_MODULE_CLASS_AD9637_interface_1 AD9637_interface

    Anyone have suggestions?
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I wish I had some more information. This problem came back for me with a single custom component. I can't seem to solve this. As a work around, you can manually place the IRQ number and IRQ controller number in the system.h file. I wish this worked because it is a headache when you are developing and regenerating your bsp.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    When either of you run into this issue is there any components between the master and slave like bridges by any chance? Likewise is the master and slave at different levels of the heirarchy? The reason why I'm asking about masters and slaves is because interrupts are tied to MM interfaces so this information might help find the culprit.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hey Omen,

    I am not using any bridges in any of my designs. I have a few simple ones that I've checked this issue out and I've seen it across all of them. As for the hierarchy I'm not sure exactly what you mean. I have a nios cpu with a custom peripheral attached to it in qsys. For example, I wrote an I2C ip core. The core works fine, but when I generate a new bsp it resets the interrupt defines discussed above to -1. I just connect the peripheral to clock, master data line and some output conduits. I attached some pics so you can see...maybe I do have a hierarchy concern and just don't realize it.

    Qsys screen:

    http://www.alteraforum.com/forum/attachment.php?attachmentid=9514&stc=1

    System.h file:

    http://www.alteraforum.com/forum/attachment.php?attachmentid=9515&stc=1

    Quartus entities:

    http://www.alteraforum.com/forum/attachment.php?attachmentid=9516&stc=1

    One thing I actually just noticed is that my interrupt line (shown in the pic where the# 2 is) is line up with my clk signal and for all of Altera's stuff it is lined up with the MM port.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Ya that interrupt being aligned to the clock is the first thing I noticed when I looked at it. I recommend taking a look at a simple component like the avalon PIO hardware .tcl file to see how it relates the interrupt to the slave port. I think you might be relating it to the clock input or nothing at all in your hardware .tcl file and that might be the culprit. The reason why it needs to be related to the slave port is so that software knows which slave port it's going to be accessing to clear the interrupt (imagine having multiple copies or a component with multiple slave ports and that's why this is necessary). So I think due to a lack of that associating when the system.h is generated when it comes across the slave port it doesn't think that there is an interrupt paired up with it.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hey guys,

    So I've got some updates as I've finally gotten my IP component working and the Eclipse SBTs have been building my system.h file with IRQ and IRQ_CONTROLLER numbers that match my Qsys design. If you look at my above post you can see my IRQ line is even with my clock input for my I2C component which is wrong (pointed out by BadOmen). I think this was due (as mentioned by two guys on the first page of this thread) to my 

    
set_interface_property s1_irq associatedAddressablePoint ""

    being blank. I added my addressable point: 

    
set_interface_property s1_irq associatedAddressablePoint "s1_irq"

    which I got from the last line here, line add_interface_port etc... 

    
add_interface s1_irq interrupt end
set_interface_property s1_irq associatedAddressablePoint "s1"
set_interface_property s1_irq associatedClock clock
set_interface_property s1_irq associatedReset reset
set_interface_property s1_irq ENABLED true
set_interface_property s1_irq EXPORT_OF ""
set_interface_property s1_irq PORT_NAME_MAP ""
set_interface_property s1_irq CMSIS_SVD_VARIABLES ""
set_interface_property s1_irq SVD_ADDRESS_GROUP ""
add_interface_port s1_irq avs_s0_irq irq Output 1

    Once I changed this you can see my IRQ line is now moved down to my Avalon MM interface. IRQ3

    http://www.alteraforum.com/forum/attachment.php?attachmentid=9531&stc=1

    After I synthesized this and rebuilt the HAL bsp my interrupt numbers came up: 

    
/*
 * I2C_Master_RXTX configuration
 *
 */
# define ALT_MODULE_CLASS_I2C_Master_RXTX I2C_Master_RXTX# define I2C_MASTER_RXTX_BASE 0x0# define I2C_MASTER_RXTX_IRQ 3# define I2C_MASTER_RXTX_IRQ_INTERRUPT_CONTROLLER_ID 0# define I2C_MASTER_RXTX_NAME "/dev/I2C_Master_RXTX"# define I2C_MASTER_RXTX_SPAN 16# define I2C_MASTER_RXTX_TYPE "I2C_Master_RXTX"

    I think this problem shows up in Qsys when you create your IP component. Check the Associated addressable interface out under your IRQ sender interface when building the component. I think you want this:

    http://www.alteraforum.com/forum/attachment.php?attachmentid=9532&stc=1

    The problem I had is that the drop down never had my interface. It only had none. So I guess setting the addressable point in the .tcl file as recommended by the guys earlier in this posts fixes this.

    Hope this is helpful!

    Rob