Honored Contributor
Honored ContributorHey Omen,
I am not using any bridges in any of my designs. I have a few simple ones that I've checked this issue out and I've seen it across all of them. As for the hierarchy I'm not sure exactly what you mean. I have a nios cpu with a custom peripheral attached to it in qsys. For example, I wrote an I2C ip core. The core works fine, but when I generate a new bsp it resets the interrupt defines discussed above to -1. I just connect the peripheral to clock, master data line and some output conduits. I attached some pics so you can see...maybe I do have a hierarchy concern and just don't realize it. Qsys screen: http://www.alteraforum.com/forum/attachment.php?attachmentid=9514&stc=1 System.h file: http://www.alteraforum.com/forum/attachment.php?attachmentid=9515&stc=1 Quartus entities: http://www.alteraforum.com/forum/attachment.php?attachmentid=9516&stc=1 One thing I actually just noticed is that my interrupt line (shown in the pic where the# 2 is) is line up with my clk signal and for all of Altera's stuff it is lined up with the MM port.
