compact flash

Hi Stebla,

I'm not familiar with the Strtix DSP kit so I can't comment on that. On our custom board we run 5 address lines to the CF connector. A0 to A2 go to the obvious places and we connect A3 and A4 to CS0 and CS1 respectively. The unused address lines on the connector (A3 to A10) are all tied low.

We power the CF with 3.3v using a 3.3v version of the LP2981 switchable regulator fed from 5v the rail. We don't have any problems although we did initally find that removing the power by turning the regulator off was insufficient, there appeared to be enough leakage current through the other lines to power the card. Your RD, WR, RESET, D0-D15 and A0-A4 should be AND'ed with the power control so everything goes low when the power is supposed to be off.

I hope this helps.

Banx.

Hi Banx,

Since you drive -CS0 and -CS1 with some address lines, does this mean that you have your own compact flash component in the pld, you don't use the SOPC Builder cf component?

stebla

Stebla,

Thats right, some user logic on an Avalon bus. The ports just include address[4..0], data[15..0], read_n, write_n and CS_n. All input except data which is inout. The CS is ORed with each of the address lines before they go to the CF connector, it doesn't go to the connector itself. I didn't design this part so I don't know the reasoning behind it but it is simple and it certainly works.

By coincidence, on another thread, I was talking to someone about having to change the bus timings recently because of the emergence of faster cards. Most cards work when setup=15nS, wait=60nS and hold=30nS (my granularity is 15nS).

Banx.

Hi Banx,

I'm using Altera's cf component in SOPC Builder, and there are no bus-timing parameters exposed when the component is instantiated. Presumably, this means that I may hit the timing problem with larger cards in the future?

Another thing is puzzling me, I don't understand why one needs to be able to switch power to the cf card if it is always to be used in true IDE mode? The Altera DSP kit uses a power mosfet and you have explained that you use a switchable 3.3V regulator driven from 5V. The cf spec says that a cf card samples the atasel# line on pin 9 on the transition from power off to power on; if atasel# is low the cf card is in IDE mode. I'm only using my cf card to be an IDE disc for my system, so I reasoned that I ought to be able to throw out the mosfet/switchable regulator on the target board that I'm designing and just permanently connect the cf card to Vcc=3.3V. However, I've just done a test on my DSP kit by forcing the cf power to be always on by going,

assign cf_power=1'b1

assign cf_atasel=1'b0;//Forced atasel low after reading Nios II 6.0 errata.pdf

and the Nios II IDE cf example that shipped with the DSP kit (essentially Jesse's software I think) says that it cannot initialize the cf. However, if I allow the cf_power signal free to toggle, the cf card works.

stebla

When I wrote,

"there are no bus-timing parameters exposed when the component is instantiated."

I did not realise that it is possible to edit the class.ptf file associated with the component in SOPC Builder. Hitherto, I had assumed that if you needed to tune up an SOPC Builder component you had to use a parameter statement in the Verilog.

stebla