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Altera_Forum's avatar
Altera_Forum
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19 years ago

compact flash

I'm designing a target board using a nios2 with compact flash as the IDE hard-drive. I've looked at the schematic for the compact flash hardware on the Stratix II DSP kit to more or less copy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

When I wrote,

"there are no bus-timing parameters exposed when the component is instantiated."

I did not realise that it is possible to edit the class.ptf file associated with the component in SOPC Builder. Hitherto, I had assumed that if you needed to tune up an SOPC Builder component you had to use a parameter statement in the Verilog.

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