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Altera_Forum
Honored Contributor
Honored Contributorcompact flash
I'm designing a target board using a nios2 with compact flash as the IDE hard-drive. I've looked at the schematic for the compact flash hardware on the Stratix II DSP kit to more or less copy...
Altera_ForumHonored Contributor
Honored ContributorStebla,
Thats right, some user logic on an Avalon bus. The ports just include address[4..0], data[15..0], read_n, write_n and CS_n. All input except data which is inout. The CS is ORed with each of the address lines before they go to the CF connector, it doesn't go to the connector itself. I didn't design this part so I don't know the reasoning behind it but it is simple and it certainly works. By coincidence, on another thread, I was talking to someone about having to change the bus timings recently because of the emergence of faster cards. Most cards work when setup=15nS, wait=60nS and hold=30nS (my granularity is 15nS). Banx.
