Honored ContributorHi,
Does anyone know how many clock cycles IORD instruction needs? It looks like 2, but I would like to clarify it. If it is 2, does mm_slave_read stay high for both clock cycles? This influences whether I need to make changes to my code. Thanks in advance.
Honored ContributorHello,
The number of cycles depends on the slave. It could take just 1 cycle if the slave allows it. You can also have a fixed number of wait states, or variable wait states if the slave implements the waitrequest signal. In your case it looks like you have one wait state inserted. In any case, the read signal does remain high throughout the read. The Avalon MM Interface Specification gives timing diagrams for various cases. CheersHonored ContributorUpon further reflection, the situation is more complicated than I previously suggested. I was thinking of it in terms of the Avalon transfer from your Slave, but the IORD macro may generate other instructions to set up the source address for the load instruction. Also, depending on the version of the core selected, the instruction can take more than 1 cycle to execute. However, I would still say that the actual Avalon transfer between the CPU and your slave will be determined by the wait states (if any) you specify, so could be a single cycle and the read signal would be active for the duration of the Avalon transfer.
Honored Contributornot only waitstates are important - also the data bus size is critical.
16-bit memory slave chip connected to the 32-bit avalon bus will drive at least 2 full 16 read cycles to gather 32 bit of data, even in the zero-waitstate situation. the number of cycles will strongly depend on the hardware configuration of the interface. if not sure, please quote the fragment of your slave declaration from the system.h file and we will help you answer this question more preciselly.
