Clock cycles per IORD instruction

Hello,

The number of cycles depends on the slave. It could take just 1 cycle if the slave allows it. You can also have a fixed number of wait states, or variable wait states if the slave implements the waitrequest signal. In your case it looks like you have one wait state inserted.

In any case, the read signal does remain high throughout the read. The Avalon MM Interface Specification gives timing diagrams for various cases.

Cheers