Clock cycles per IORD instruction

not only waitstates are important - also the data bus size is critical.

16-bit memory slave chip connected to the 32-bit avalon bus will drive at least 2 full 16 read cycles to gather 32 bit of data, even in the zero-waitstate situation.

the number of cycles will strongly depend on the hardware configuration of the interface.

if not sure, please quote the fragment of your slave declaration from the system.h file and we will help you answer this question more preciselly.