Clock cycles per IORD instruction

Upon further reflection, the situation is more complicated than I previously suggested. I was thinking of it in terms of the Avalon transfer from your Slave, but the IORD macro may generate other instructions to set up the source address for the load instruction. Also, depending on the version of the core selected, the instruction can take more than 1 cycle to execute. However, I would still say that the actual Avalon transfer between the CPU and your slave will be determined by the wait states (if any) you specify, so could be a single cycle and the read signal would be active for the duration of the Avalon transfer.