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Honored ContributorCan't Read Data from Custom componet (Avalon mm)
I had associated a custom component (A variation of the DCFIFO example available in AN 473) to my NIOS 2 System. I use the Avalon MM (Slave) Interface whit the current signals:
Readdata (32bits) out Read (Used as the component read clock) IN Everything goes right to me, till i try to read some data from the nios 2 software. (I use the HAL, avoiding any OS) I can find the base address in System.h#define DCFIFO_DE_TOP_0_NAME "/dev/dcfifo_de_top_0"# define DCFIFO_DE_TOP_0_TYPE "dcfifo_de_top"# define DCFIFO_DE_TOP_0_BASE 0x00400000# define DCFIFO_DE_TOP_0_SPAN 4# define DCFIFO_DE_TOP_0_TERMINATED_PORTS ""# define ALT_MODULE_CLASS_dcfifo_de_top_0 dcfifo_de_top
IORD(DCFIFO_DE_TOP_0_BASE,0);27 Replies
Altera_ForumLuirro had posted a new verilog code that implements the smaller avalon mm slave device that we can make.
This is the HDL: pastebin.com/yMBeTWPz We conect it to the sopc, assigning the following pins: Clk ==> clk_sink irq_port ==> interrupt sender ==> irq data_o ==> Avalon_Slave ==> readdata read_i ==> Avalon_Slave ==> read We have declare the ISR, but nothing happens, if we force the reading, only zeros again... The componet works perfect. Any ideas? Jairo- Altera_Forum
When Jairo says "the component works perfect", he means that we've simulated the HDL (in quartus and modelsim) and it works like we want it does.
Regards. - Altera_Forum
Ok, there is a simpler code:
This only puts a constant on readdata whatever the inputs are. And there is the Nios2 sofware side... it still reads Zeros...module simpler ( data_o, address_i, clk, read_i ); output reg data_o; input address_i; input clk; input read_i; always @ (posedge clk) begin data_o = 32'hF0F0F0F0; end endmodule
sorry for being so annoying#include "basic_io.h"# include "Test.h"# include "LCD.h"# include "DM9000A.C" int main(void) { unsigned int res, i; for(i=0; i < 255; i++) { res = IORD(SIMPLER_0_BASE, 0x00); printf("\nIteracion %d, res =%d", i, res); msleep(500); } return 0; } - Altera_Forum
That's really strange... Are you sure that your component is connected to the Nios data master port? In the component editor, are you sure that data_o is defined as readdata on the slave interface?
- Altera_Forum
Hi again,
I just read your thread again. I´m not really sure wheres your problem but I wanted to help you. I created a really simple read & write component for SOPC builder. I attached the screen of the SOPC, the main.c programm I tested the component with and the Verilog file with the tcl file. If you use the component with my tcl you should not get any problems to read or write from it. - Altera_Forum
Hi Jacol... thanks a lot.
A question: Did you build your SOPC design from zero? O did you just adapt an existing design? Regards - Altera_Forum
I don't know what's happening but we test you design and it doesn't work. Can you send me the entire project??
my email es jairotrad (at) gmail (dot) com Greetings! - Altera_Forum
Hi guys.
Finally, we could make our project worked. We did it!! Thanks everyone.... but, now we have another problem. We want our device to work as an interrupting one. So, we wrote a code as follows: pastebin.com/U3xfZXrY And this is our modified HDL: pastebin.com/Xypads8f We simulated it, and it apparently works, but when we want to run at NIOS EDS, it doesn't work.. Any suggestions? Thanks a lot!!! - Altera_Forum
About your C code:
you shouldn't call printf() from an ISR. It will probably try also to use interrupts, and it can freeze the system. Instead, define a global variable, change its value inside the isr, put the printf() in your main() function and have it print something when the contents of the global variable changes. About your Verilog code: put everything inside the always @ (posedge clk_i) block. You shouldn't use the signal read_i as a clock. Instead, detect changes in read_i by comparing it to its previous value inside the main block that depends on clk_i. Using a signal as a clock will lead to all kind of problems on your design, including transitions at unwanted moments due to glitches. - Altera_Forum
Hi daixiwen.
Our problem is: we need to detect the change of the signal read_i. 1) We send a irq request. 2) The Avalon Master detects our request, so, it asserts the read_i and we need to desassert irq_req. 3) When the device stops the reading, it dessaserts read_i, and then we have to go to INCADR state, to get the next data from a FIFO and putting it as output. I can't understand how I could do it the way you said. Thanks.
