Can't Read Data from Custom componet (Avalon mm)

Hi,

what happens if you are using the memory window on the baseadress of your component? Are there only zeros, too? What setting have you done for your component in sopc? I mean the interface and timing in the sopc-builder (setup, read wait, write wait, etc.)? If you think write is ok and read makes trouble I would try to raise read wait.

Here you can see the input ouput Configuration

i53.tinypic.com/dlq235.jpg (http://i53.tinypic.com/dlq235.jpg)

An Here the settings for the avalon interface.

i56.tinypic.com/2vshlpv.jpg (i56.tinypic.com/2vshlpv.jpg)

We have changed the configuration to a IRQ Drived one. But despite we register the ISR the Software doesn't detect anything...

I' have no idea about what is the problem... Any help will be good.

Hi,

you only have connected read and readdata. So the only thing you can do from Nios-side is read the data. Which values you want to read? If you have choosen "No, leave it blank" in "Mem Init" due the RAM initialisation there will only be zeros in it. How do you get something in the RAM?

Hi.

I'm the Jairo's partner. I'm sending you our HDL. It's based on AN 473: Using DCFIFO for Data Transfer between Asynchronous Clock Domains.

Regards!!!

I don't use Verilog but from what I'm understanding in the read control logic it seems that you read the contents of the FIFO as soon as there is something in it, even if there isn't a read request coming on your component. Is that really what you want?

It could be a good idea to use SignalTap to look at your signals and understand what is happening.

Hi,

I´m not sure but for me it looks like you don´t come back to IDLE. You only go from INCADR->WRITE->WAIT->INCADR. Is that your intention?

Hi.

We've created a new simpler design. It consist in a state machine that puts a constant value at output, handled by some control signals.

This is the HDL:

pastebin.com/yMBeTWPz

We have been simulating it, and it seems to works in the way we want. Now, we just need to test it with SOPC and NIOS II IDE. It's been a long week for us. We'll do it on Tuesday.

Any suggestion will be welcome.

Regards.

This is a basic observation, so maybe I am missing something. I haven't read any of your verilog code, but you wrote that your C code was:

IORD(DCFIFO_DE_TOP_0_BASE,0);

You are not assigning it to any variable, like:

unsigned int result;

result = IORD(DCFIFO_DE_TOP_0_BASE,0);

How do you know that the IORD is returning nothing but zero? Are you stepping through the assembly code?

After further examination of the verilog code in read_control_logic, like someone else pointed out:

"I´m not sure but for me it looks like you don´t come back to IDLE. You only go from INCADR->WRITE->WAIT->INCADR. Is that your intention?"

I concur. Not to mention that having a state named "WRITE" in a module called read_control_logic doesn't seem like a good practice, as you aren't writing anyting, and doesn't describe what you are attempting to do.

On the statement:

"always @ (posedge clk_i or posedge reset_i or negedge read_i) begin"

the "or negedge read_i" part bothers me. I've never used that as a condition in an always.

"assign data_o = data_i" bothers me.

You do nothing with data_i in your code, so why pass it in and out? In dcfifo_de_top3.v, I would rename "q" as readdata, and put "assign readdata = fifo_out;" somewhere, and take out the unused ports of "data_i" and "data_o" in read_control_logic.v

Overall, I would suggest you try experimenting with the simplest avalon MM slave you can think of first (like returning a constant), verify you read the result, then progress in baby steps. You seem like you are trying to do too much at once for your level of understanding.