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Altera_Forum
Honored Contributor
15 years agoHi.
We've created a new simpler design. It consist in a state machine that puts a constant value at output, handled by some control signals. This is the HDL: pastebin.com/yMBeTWPz We have been simulating it, and it seems to works in the way we want. Now, we just need to test it with SOPC and NIOS II IDE. It's been a long week for us. We'll do it on Tuesday. Any suggestion will be welcome. Regards.