Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThis is a basic observation, so maybe I am missing something. I haven't read any of your verilog code, but you wrote that your C code was:
IORD(DCFIFO_DE_TOP_0_BASE,0); You are not assigning it to any variable, like: unsigned int result; result = IORD(DCFIFO_DE_TOP_0_BASE,0); How do you know that the IORD is returning nothing but zero? Are you stepping through the assembly code? After further examination of the verilog code in read_control_logic, like someone else pointed out: "I´m not sure but for me it looks like you don´t come back to IDLE. You only go from INCADR->WRITE->WAIT->INCADR. Is that your intention?" I concur. Not to mention that having a state named "WRITE" in a module called read_control_logic doesn't seem like a good practice, as you aren't writing anyting, and doesn't describe what you are attempting to do. On the statement: "always @ (posedge clk_i or posedge reset_i or negedge read_i) begin" the "or negedge read_i" part bothers me. I've never used that as a condition in an always. "assign data_o = data_i" bothers me. You do nothing with data_i in your code, so why pass it in and out? In dcfifo_de_top3.v, I would rename "q" as readdata, and put "assign readdata = fifo_out;" somewhere, and take out the unused ports of "data_i" and "data_o" in read_control_logic.v Overall, I would suggest you try experimenting with the simplest avalon MM slave you can think of first (like returning a constant), verify you read the result, then progress in baby steps. You seem like you are trying to do too much at once for your level of understanding.