Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI don't use Verilog but from what I'm understanding in the read control logic it seems that you read the contents of the FIFO as soon as there is something in it, even if there isn't a read request coming on your component. Is that really what you want?
It could be a good idea to use SignalTap to look at your signals and understand what is happening.