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Altera_Forum's avatar
Altera_Forum
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12 years ago

Can't ping:TSE+DP83848K+RMII

Dear all,

Recently I debug the board designed by myself. I use dp83848K and take the rmii mode.

I got the rmii to mii code from Daixiwen.

Now I can't ping my board.

I've test the mac_rxd[4..0] and compare the data with wireshark. It is correct,this means data transmit to mac. I'm confused about the interface between rmii_mii model with tse_mac.

https://www.alteraforum.com/forum/attachment.php?attachmentid=7600

https://www.alteraforum.com/forum/attachment.php?attachmentid=7599

https://www.alteraforum.com/forum/attachment.php?attachmentid=7601

https://www.alteraforum.com/forum/attachment.php?attachmentid=7602

https://www.alteraforum.com/forum/attachment.php?attachmentid=7603

Could anyone give me some direction? Thanks a lot!

The message from Nios IDE 12.1:

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Can't read the MAC address from your board (this probably means

that your flash was erased). We will assign you a MAC address and

static network settings

Can't read the MAC address from your board. We will assign you

a MAC address.

Your Ethernet MAC address is 00:07:ed:ff:00:01

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x02002000

INFO : PHY National DP83848C found at PHY address 0x01 of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 100, Duplex = Full

OK, x=0, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x04000203

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

mctest init called

IP address of et1 : 192.168.1.234

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up

[sss_task] Simple Socket Server listening on port 30

Created "simple socket server" task (Prio: 4)

17 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    In the qsys, I connect the sgdma_pipeline to SDRAM,and then use dma connect it to Nios cpu.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Try to use Signaltap to debug the system. Check first that when you get a packet on mac_rxd[4..0], that you also get it out on the MAC's Avalon Stream RX interface.

    Check also that the receive SGDMA is working. It should read the first descriptor when the system initializes, and when a packet arrives on the Avalon Stream interface, it should read it and write it to m_write.

    I see that you are using descriptor memory blocks, is the driver configured correctly to use them?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you,Daixiwen.

    I use signaltap to watch the mac_rxd and mac_rx_dv,but no signal can be captured. So I set these signals to others iOS and watch them by oscillator. The four bits frame are as same as the wireshark's display.

    Now I don't know how to watch the red in tse or sgdma_rx. I still confused with the 'mac_rx_dv', currently I connect the signal to rx_col in tse_mac. I'm not sure this step.

    Besides I read the data sheet of DP83848K, it says loop back can be completed by connect rx_dv to tx_en,rxd to Txd.

    Best regards.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    The mac_rx_dv is the "data valid" signals and indicates when the data on mac_rxd[] is valid. It should be connected to the mac's m_rx_en port, not m_rx_col. But this doesn't explain why you don't see anything on SignalTap. Put a positive edge trigger on mac_rx_dv, and if it never triggers, it means either that the PHY isn't receiving a packet or that it isn't connected correctly to the FPGA. In that case you can try to put some Signaltap probes on the rmii side of the interface and see if anything is happening there.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thank you very much. I have solved the problem.

    But I try to catch the mac_rxd signal in signaltap, and I choose 100M clock source.The result doesn't display.

    I use the Altera example and get success.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I'm confused. Is the problem solved or not? What do you mean by "doesn't display"? Did you set the trigger on m_rx_en? Is it triggering?

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I have solved the problem.but I can't get the signal by signaltap,maybe my usb-blaster doesn't work well.

    Thank you again.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Could you define "can't get the signal"? Please give _a lot_ more details about what you did and what you observe.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    I have solved the problem.but I can't get the signal by signaltap,maybe my usb-blaster doesn't work well.

    Thank you again.

    --- Quote End ---

    Please what have you did when you have solved the problem? I have similar problem.. My connection of the RXDV is correct.. Thank you for your kind answer.