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Altera_Forum's avatar
Altera_Forum
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20 years ago

Can't launch debugger

When starting 'Debug as NIOS II Hardware' from IDE (Version 5.0), I always get the following message: 

Downloading 00000000 ( 0%)      (-> this is EPCS)
Downloading 00005000 ( 0%)      (-> this is internal ROM)
Downloading 00200020 ( 0%)      (-> this is System-RAM, where firmware should run)
Downloading 00210000 (26%)
Downloading 00220000 (52%)
Downloading 00230000 (78%)
Downloaded 247KB in 5.6s (44.1KB/s)
Verifying 00000000 ( 0%)
Verify failed                                 ( -> ERROR )
Leaving target processor paused
Suspect is, that at address 0 where this verifying error occurs, an EPCS device is present. This EPCS contains the FPGA configuration (at address 0 !) and a short loader firmware behind. The firmware, I want to debug, is loaded at 0x00200020, a SRAM.

- Is the debugger able to load and verify the contents of EPCS ?

- Is it possible, to suppress this verifying or remove this part from download ?

Mike

later added:

there is another topic concerning the same problem: ... same problem at onother topic (http://www.niosforum.com/forum/index.php?act=st&f=2&t=1752)

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Mike,

    If you're using the default EPCS controller, it doesn't allow linear access to the EPCS's contents and only contains some bootloader code (in onchip memory). Take a look at your memory map, for the controller, and you'll see what I mean.

    I had this misunderstanding when I first looked at the EPCS controller, as well. Please read the docs. on the EPCS controller. Oh yeah, because of this, it will not be possible to run code from the EPCS controller, which _may_ be what you're trying to do.

    There is a 3rd. party EPCS controller, available here (http://www.fpga.nl/ipcores.html), which should allow you to "see" the contents of the cpu's masters to "see" the EPCS, in a linear fashion.

    Cheers,

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    slaker,

    I understand what you mean. But obviously the debugger doesn't 'know' how data in EPCS is organized, if EPCS contains both configuration data and firmware. The messages appear when launching the debugger from IDE which is set to: 'Download Program to RAM'. ... see parallel topic (http://www.niosforum.com/forum/index.php?act=st&f=2&t=1752)

    Mike
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Mike,

    Neither the debugger, nor the CPU "know" how the data is organized in the EPCS. If you set the reset location (in SOPC Builder) to be in the EPCS device, it will run boot-copier code (in "ON CHIP/ON FPGA" memory) which will copy your code from the EPCS device into memory. Perhaps, you're epcs_controller_boot_rom.hex file got hosed and/or you've not been through a compile/programming cycle in a while?? Then again, I'm not sure why the debugger is trying to check code at 0x0, either... which leads to the next question:

    What settings are you using, in SOPC Builder and/or the IDE? (i.e.: reset/exception location in SOPC Builder and where you're running code from in the IDE)

    Cheers,

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    slacker,

    my problem is not generating a running system. It all runs. The problem only arises, when debugger loads and tries to verify parts of program data. I think there is a malfunction of this download, because the section, which is compiled and linked at address 0 (restart vector is set to EPCS) is originally programmed into EPCS but at a higher address. At address 0 there is FPGA configuration. So, when launching debugger, the verify process should skip EPCS data, because its contents is relocated by the boot-copier, as you described and not placed at the address its origin (from .elf file) suggests. And this problem is new since Version 5.0.

    Jesse has posted an explanation of this issue in ... parallel topic (http://www.niosforum.com/forum/index.php?act=st&f=2&t=1752).

    Thanks for your hints

    Mike
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    slacker,

    you are right, and I have to correct my statement: the EPCS content isn't seen in the address space of NIOS. Direct accessible is the EPCS-controller. A memory dump at address 0 shows the code of 'epcs_controller_boot_rom.hex', the boot-copier ROM. But when compiling and linking my firmware, an .entry section is created, and a restart code automatically generated. And this is what the debugger expects, when downloading. So verifying will always fail.

    Thanks for your help

    Mike