Mike,
Neither the debugger, nor the CPU "know" how the data is organized in the EPCS. If you set the reset location (in SOPC Builder) to be in the EPCS device, it will run boot-copier code (in "ON CHIP/ON FPGA" memory) which will copy your code from the EPCS device into memory. Perhaps, you're epcs_controller_boot_rom.hex file got hosed and/or you've not been through a compile/programming cycle in a while?? Then again, I'm not sure why the debugger is trying to check code at 0x0, either... which leads to the next question:
What settings are you using, in SOPC Builder and/or the IDE? (i.e.: reset/exception location in SOPC Builder and where you're running code from in the IDE)
Cheers,
- slacker