booting a dual NIOS II

Question

So, I&amp;#39;ve been working on this 1S10 dev board.   I&amp;#39;ve twice gotten dual core builds that loaded from different addresses on flash. Last time I added other items that pushed the size (LEs) over the chip limit but after removing other devices like SDRAM, could not get back to booting. So I started from a saved version and retraced my steps to a "now - as of yesterday" dual booting version. Would you say that a dual core should boot from flash properly without changing supporting files (generated.x) - just using the IDE with mods only to the "more settings" SOPC B flash (reset) address and the target device (exception) address (and system lib properties target addresses)?   I ask because it has worked twice that way for me and I&amp;#39;m wondering if I can count on it. Oh, I&amp;#39;m running one cpu from SRAM and the other from an on-chip 64k ram. Booting from 0 and 0x200000. I understand the support is being added in the next rev. - just wondered if anybody had any thoughts about the inconsistency I experienced. Did I screw something up, maybe?   Thanks. And thanks Kerri for working my customer support stuff.

altera_forum · Answer

Hi all !!!

I have a dual Nios II core system with on_chip_memory1, on_chip_memory2 and flash.

I prepared also 2 C++ Application in Nios II IDE, for cpu1 and cpu2.

How can I use the options to build a project that loads from different addresses on flash, transferring the two codes from the flash to each on_chip_memory??? http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif

Is it possible??

Bye!

altera_forum · Answer

When creating the cpus under the more "cpu" settings, you have to specify the Reset Address and Exception Address. Reset is where in flash you put your program and Exception is where you want to execute from (target device like onchip ram or sram). I choose cpu 1 to boot from ext_flash at 0 and run from sram at device address + 0x20. The second cpu boots from ext_flash at 0x00200000 (where i put the second executable using the flash programmer) and runs from onchip at device address + 0x20. In my project settings under NIOS II IDE I choose the cpu 1 system lib to reside in ext_ram with normal library settings. Cpu 2 lib resides in onchip and I chose small C lib support to fit the program into 64K. I used the flash programmer to put cpu1 code into flash at 0 along with the FPGA image and then put cpu2 code into flash at 0x200000. I&amp;#39;ve had pretty good success with 2 cores. Adding Dual Port Ram and multiple serial ports has given me some grief - like my second cpu stops booting or DPR doesn&amp;#39;t work consistently - stuff like that.  But overall, it&amp;#39;s pretty cool. You should probably read Kerri&amp;#39;s post on adding the second core and setting up the environment correctly - this entry just builds on her post.

altera_forum · Answer

Thank you for your answer! I&amp;#39;ll try your advices as soon as possible.  Sorry, I would like to know another thing: have you used only the GUI or also the nios2-flash-programmer command line???   Bye!  http://forum.niosforum.com/work2/style_emoticons/&lt;#EMO_DIR#&gt;/wink.gif

altera_forum · Answer

I have only used the NIOS IDE to do development thus far.

altera_forum · Answer

Do you thing is possible to configure the system in this way?:

It doesn't work to me!!! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif

CPU1:

reset address: FLASH 0x00000000

exception address: SDRAM 0x00000020

CPU2:

reset address: FLASH 0x00200000

exception address: SDRAM 0x00800020

PS: I have 1S40; Flash = 8 MB and SDRAM = 16 MB

Bye!!!

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booting a dual NIOS II

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