2 read pulses after an IORD_16DIRECT

Yes, this is pretty normal.

If you search the forum you'd find other threads related to this issue.

Avalon bus always performs a complete 32bit access, even if you limit the required data to 16 or 8 bit. Then, with a IORD_8DIRECT you'd get 4 read pulses.

I had once a situation similar to yours where a fifo register was involved and the second read pulse was to be avoided. I solved it with the following trick:

- extend the sram interface to 32bit, but connect only 16 lower bits

- shift sram address lines in order to match 32bit addressing

- IORD_32DIRECT and discard the upper 16bits

A more clever solution would involve gating the read pulse according to address, I mean the rd pulse is passed to sram interface only if address is a multiple of 4; rd pulse instead is blocked if address=4*N+2

Also note that the NIOS cpu always asserts all 4 byte enables for reads.

It is a shame that the bus width adapters generate cycles with no byte enables asserted - maybe they don't know in time to skip the first cycle, but it ought to be possibly to finish early when no more transfers are needed.

Avalon Tristate bridge

Bus_Type = "avalon_tristate";

Address_Group = "1";

Has_Clock = "0";

Address_Width = "8";

Address_Alignment = "dynamic";

Data_Width = "32";

Has_Base_Address = "1";

Has_IRQ = "0";

Setup_Time = "40ns";

Hold_Time = "10ns";

Read_Wait_States = "60ns";

Write_Wait_States = "40ns";

Read_Latency = "0";

Few questions:

1) There is no byte enable pin on isp1763 (USB chip) so how are you using dynamic bus sizing?

2) If you are using native alignment, there will be 4x offset between master and slave address (niosII 32 bit and USB 16bit). All registers on the USB chip have 8 bit address so you have to multiply them by 4, they will become more than 8bit. How can you then have 8bit address for the interconnect (Avalon address)?