2 read pulses after an IORD_16DIRECT

Yes, this is pretty normal.

If you search the forum you'd find other threads related to this issue.

Avalon bus always performs a complete 32bit access, even if you limit the required data to 16 or 8 bit. Then, with a IORD_8DIRECT you'd get 4 read pulses.

I had once a situation similar to yours where a fifo register was involved and the second read pulse was to be avoided. I solved it with the following trick:

- extend the sram interface to 32bit, but connect only 16 lower bits

- shift sram address lines in order to match 32bit addressing

- IORD_32DIRECT and discard the upper 16bits

A more clever solution would involve gating the read pulse according to address, I mean the rd pulse is passed to sram interface only if address is a multiple of 4; rd pulse instead is blocked if address=4*N+2