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Altera_Forum's avatar
Altera_Forum
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13 years ago

2 read pulses after an IORD_16DIRECT

we are implementing the isp1763A on our custom board. when we do an IORD_16DIRECT at address 0x00 the system generate 2 Read pulses at address 0x00 and 0x02 ISP1763 is configured in SRAM 16bit ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Also note that the NIOS cpu always asserts all 4 byte enables for reads.

It is a shame that the bus width adapters generate cycles with no byte enables asserted - maybe they don't know in time to skip the first cycle, but it ought to be possibly to finish early when no more transfers are needed.