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Altera_Forum's avatar
Altera_Forum
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13 years ago

2 read pulses after an IORD_16DIRECT

we are implementing the isp1763A on our custom board. when we do an IORD_16DIRECT at address 0x00 the system generate 2 Read pulses at address 0x00 and 0x02 ISP1763 is configured in SRAM 16bit ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Few questions:

1) There is no byte enable pin on isp1763 (USB chip) so how are you using dynamic bus sizing?

2) If you are using native alignment, there will be 4x offset between master and slave address (niosII 32 bit and USB 16bit). All registers on the USB chip have 8 bit address so you have to multiply them by 4, they will become more than 8bit. How can you then have 8bit address for the interconnect (Avalon address)?