who can help me about PCI compiler

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I developed a SOPC which including a PCI compiler on the ALtera PCI development kit, the configuration of PCI compiler was: Host Bridge Mode, 32bit, 33MHz, BAR0 Auto, BAR1 auto, two fixed address translation table including a configuration space and a memory space.

my question is : how can i access the configuration space to read regs sucn as Device ID or Vendor ID ?

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Under what operating system?

Under Linux you simply type lspci (and then man lspci to learn more).

Under Windows, there is a tool called pcitree (and others).

PCI device drivers under Linux are pretty simple. If that is what you are interested in, then I'll post some links.

Cheers,

Dave

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Under what operating system?

Under Linux you simply type lspci (and then man lspci to learn more).

Under Windows, there is a tool called pcitree (and others).

PCI device drivers under Linux are pretty simple. If that is what you are interested in, then I'll post some links.

Cheers,

Dave

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thank you very much .

There is no os.

I just want to use the board with pci compiler as pci master, and another board connected to it as slave. Under Nios II IDE, how can i access the configuration space of master device or slave device?

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There is no os.

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Ok.

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I just want to use the board with pci compiler as pci master, and another board connected to it as slave. Under Nios II IDE, how can i access the configuration space of master device or slave device?

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Is the PCI core an Avalon component? If it is, then in your SOPC or Qsys System, there should be an Avalon-MM slave block for the configuration space, another for PCI accesses, and there may be some other registers so that the PCI accesses will use I/O or memory commands.

If the PCI core is not an Avalon component, then the same sorts of register interfaces will likely exist, its just that you'll have to create Avalon-MM interfaces, so that your SOPC system containing the NIOS core can access those registers.

I would recommend starting with a testbench of just the PCI core alone, and figure out how to get a couple of instances talking to each other, i.e., configure one as the master and one as the target.

Cheers,

Dave

One additional thing you might need is an arbiter to grant the master access to the bus when it requests it.

Or in your master design just hard wire the grant signal active.

?

Nial