TSUGI
New Contributor
New ContributorWhere is High Speed Transceiver Demo Design in FPGA Wiki ?
I can't find these demo design.
- Superlite II V4
- Superlite IV
- Soft PRBS BERT Design
- oversampling design
and so on.
Forum Discussion
10 Replies
TSUGIHi Cheepin,
I cannot download some URL on Agilex 7 F-Tile.
8. Superlite II V4 (with/without KR FEC)- New (10/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 design using 2 times 4 lanes at 25.78125 Gbps to transport 100 Gbps of raw data.
- Updated (10/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 design using 2 times 4 lanes at 10.3125 Gbps to transport 40 Gbps of raw data.
9. Superlite IV (RSFEC)
Intel Agilex® device I-Series SI/SOC Board
- NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus), total bandwidth = 4x400Gbps = 1.6 Tbps
- NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus), total bandwidth = 4x600Gbps = 2.4 Tbps
Intel Agilex® device I-Series PCIe development kit
- NEW (26/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 4 instances of 1 PHY direct IP configured in 100Gbps with KPFEC, bonded across 2 lanes at 53.125 Gbps to transport 100 Gbps of raw data (transparent transmission of a 256-bit bus), total bandwidth = 4x100Gbps = 400 Gbps.
- NEW (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus)
- Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus)
- CheepinC_altera
Regular Contributor
Hi,
Sorry for the delay. The following are the archive for Agilex F-Tile designs that I could locate. Can you help to check out. Thank you.
1. Multi-Prbs Generators and Checkers
- (28/04/2021) Collection of Multi-Prbs Generators and Verifiers used in various transceiver demo's with different bit widths: 32-bit, 64-bit, 128-bit, and 256-bit. Includes test bench as well.
2. Supporting documentation for the F-tile Demo Designs
- Soft PRBS Demo designs (with/without RSFEC)
- agilex-f-tile-demo-designs.pdf Updated (03/02/2022)
- Superlite II designs
- agilex-f-tile-superlite-ii-demo-designs.pdf Updated (09/02/2022)
- Superlite IV designs
- agilex-f-tile-superlite-iv-demo-designs.pdf Updated (18/02/2022)
3. Description of all F-tile Demo Designs (Excel file)
- Updated (15/02/2022)
- description-of-designs.xlsx (V1.6)
4. Library of C-functions for F-tile transceivers using AVMM Interfaces
- Updated (28/01/2022)
- Complete library of C-functions/drivers for F-tile
- f-tile-software.zip (V1.9)
5. Script with useful procedures for use in the system console with Agilex F-tile
- New (12/08/2022)
- Functions to be used with F-tile PHY-Direct/FEC-Direct designs/F-tile Ethernet Hard IP designs (controlling loopbacks, showing PMA settings, performing EHM, setting Media mode to VSR/Optics etc.). Requires NDME to be enabled. Supports both FGT and FHT.
- ttk-helper-ftile.tcl (V1.0)
6. Soft PRBS with RSFEC Demo Designs
Intel Agilex® device I-Series PCIe development kit
- NEW (04/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 2x200G Aggregate mode using FGT transceivers connected to QSFPDD1
- NEW (11/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4 channel 25.78125 Gbps soft PRBS test design with RSFEC (528,514) in 2x100G Aggregate mode using FGT transceivers connected to QSFPDD0 and QSFPDD1
- Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD1
- NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 200G Aggregate mode using FGT transceivers connected to QSFPDD's
- Updated (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to QSFPDD's + dynamically reconfigurable internal noise.
- NEW (11/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 3x4x1 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to QSFPDD's
- (13/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel NRZ 25.7815 Gbps soft PRBS test design with RSFEC (528,514) Fractured mode using FGT transceivers connected to QSFPDD's
Intel Agilex® device I-Series SI/SOC Board
- NEW (06/12/2021) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): 2x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0 and QSFPDD1
- NEW (06/12/2021) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile device): 1x8 channel 53Gbps PAM4 soft PRBS test design with KPFEC (544,514) in 400G Aggregate mode using FGT transceivers connected to QSFPDD0
Intel Agilex® device I-Series HS Demo Board
- (17/09/2021) Intel Agilex® device I-Series HS Demo Board (ES Version): 2x4 channel PAM4 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FGT transceivers connected to FMC+
- Updated (28/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 106 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FHT transceivers connected to OSFP800
- NEW (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel NRZ 53.125 Gbps soft PRBS test design with KPFEC (544,514) Fractured mode using FHT transceivers connected to OSFP800
7. Soft PRBS Demo Designs (no FEC)
Intel Agilex® device I-Series SI/SOC Board
- NEW (02/02/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): 2x8x1 channel 53Gbps PAM4 soft PRBS test design using FGT transceivers connected to QSFPDD0 and QSFPDD1
Intel Agilex® device I-Series PCIe development kit
- Updated (31/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's with dynamically reconfigurable internal noise logic.
- (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel NRZ 25.78125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's
- agilex-pcie-devkit-prbs-2x4x1ch-ftile-26gbps.zip (21.3 B170)
- (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 2x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's
- agilex-pcie-devkit-prbs-2x4x1ch-ftile-53gbps.zip (21.3 B170)
- (08/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 3x4x1 channel PAM4 53.125 Gbps soft PRBS test design using FGT transceivers connected to QSFPDD's
- agilex-pcie-devkit-prbs-3x4x1ch-ftile-53gbps.zip (21.3 B170)
Intel Agilex® device I-Series HS Demo Board
- (20/09/2021) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x4 channel NRZ 25.78125 Gbps soft PRBS test design using FGT transceivers connected to FMC+
- Updated (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 53.125 Gbps soft PRBS test design using FHT transceivers connected to OSFP800
- NEW (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel NRZ 53.125 Gbps soft PRBS test design using FHT transceivers connected to OSFP800
- Updated (26/01/2022) Intel Agilex® device I-Series HS Demo Board (ES Version): 4x1 channel PAM4 106 Gbps soft PRBS test design using FHT transceivers connected to OSFP800
8. Superlite II V4 (with/without KR FEC)
- New (10/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 design using 2 times 4 lanes at 25.78125 Gbps to transport 100 Gbps of raw data.
- NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 with soft KR-FEC Demo design using 2 times 4 lanes at 10.3125 Gbps to transport 40 Gbps of raw data
- agilex-pcie-devkit-superliteii-v4-soft-krfec-ftile-fgt-2x4-lanes.zip (21.4, can be programmed using 21.3)
- Updated (10/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite II V4 design using 2 times 4 lanes at 10.3125 Gbps to transport 40 Gbps of raw data.
9. Superlite IV (RSFEC)
Intel Agilex® device I-Series SI/SOC Board
- NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus), total bandwidth = 4x400Gbps = 1.6 Tbps
- NEW (18/01/2022) Intel Agilex® device I-Series SI/SOC Board (ES Version) (4 F-tile devices): Superlite IV design using 4 instances (one per F-Tile) of 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus), total bandwidth = 4x600Gbps = 2.4 Tbps
Intel Agilex® device I-Series PCIe development kit
- NEW (26/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 4 instances of 1 PHY direct IP configured in 100Gbps with KPFEC, bonded across 2 lanes at 53.125 Gbps to transport 100 Gbps of raw data (transparent transmission of a 256-bit bus), total bandwidth = 4x100Gbps = 400 Gbps.
- NEW (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 3 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 12 lanes at 53.125 Gbps to transport 600 Gbps of raw data (transparent transmission of a 1,536-bit bus)
- Updated (18/01/2022) Intel Agilex® device I-Series PCIe development kit (ES Version): Superlite IV design using 2 times a PHY direct IP configured in 200Gbps with KPFEC, bonded across 8 lanes at 53.125 Gbps to transport 400 Gbps of raw data (transparent transmission of a 1,024-bit bus)
10. 400GbE
- (8/10/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 400GbE (400G-8) Example Demo design using QSFPDD1
- (8/10/2021) Intel Agilex® device I-Series HS Demo Board (ES Version): 400GbE (400G-4) Demo design using OSFP800
- agilex-hs-demo-400gbe-4-fht-example-design.zip (21.3 B170)
11. 100GbE
- NEW (30/11/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 100GbE (100G-4) with RSFEC(528,514) 4x25.78125 Gbps Example Demo design using QSFPDD1
12. 25GbE
- NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 25GbE (25G-1) with RSFEC(528,514), Single lane Example Demo design using QSFPDD1
13. 10GbE
- NEW (06/12/2021) Intel Agilex® device I-Series PCIe development kit (ES Version): 10GbE (10G-1), Single lane Example Demo design using QSFPDD1
- TSUGI
Thank you, I'll check these S10 Designs.
How about these Reference Designs for Agilex 7 F-Tile ?
- CheepinC_altera
Hi TSUGI,
Sorry for the delay. Seems like there is a glitch with the system recently which is causing issue for me to add new post.
For your information, I managed to locate a few S10 Superlite IV design links after consulting the admin. Would you mind to check if you are able to download them using the following links? Please let me know if there is any concern. Thank you.
6. Superlite IV (using Native PHY) (with FEC)
PAM4
- Updated (27/04/2021) Stratix 10 TX SI Board (Prod) : 1.8Tb Superlite IV Demo design using 18 times 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (+ I2C) (Native PHY + KPFEC)
- (12/02/2019) Stratix 10 TX SI Board (S1) : 100G Superlite IV Demo design using 2 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 100 Gbps of raw data (Native PHY + KPFEC)
- (17/04/2019) Stratix 10 TX SI Board (S1) : 400G Superlite IV Demo design using 8 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 400 Gbps of raw data (+ I2C & Fan Control + tested with 400G Optics) (Native PHY + KPFEC)
- (13/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC)
- (08/03/2019) Stratix 10 TX SI Board (S1) : 1.8Tb Superlite IV Demo design using 3 times 12 lanes at 53.125 Gbps with PAM4 encoding and KP-FEC to transport 1.8Tbits of raw data (Native PHY + KPFEC)
NRZ
- (19/02/2019) Stratix 10 TX SI Board (S1) : 600G Superlite IV Demo design using 24 lanes at 25.78125 Gbps with NRZ encoding and RS-FEC to transport 600 Gbps of raw data (Native PHY + KPFEC)
MichaelYaoHi, I am also looking for these designs. They were available in Intel community before. Please help. Thanks.
- CheepinC_altera
Hi,
Thanks for reaching out. I understand you have some inquiries related to high-speed design content that was previously available on the FPGA Wiki.
To assist you better, could you please specify which particular demo design you are looking for? Once I have more details, I will check internally to see if can help locate the relevant design.
Feel free to share any additional concerns. Thank you.
- TSUGI
I need ...
- Superlite II V4 Design for Agilex 7 F-Tile and Stratix 10 GX and Arria 10 GX.
- Superlite IV Design for Agilex 7 F-Tile and Stratix 10 GX and Arria 10 GX.
- Soft PRBS BERT Ref.Design for Agilex 7 F-Tile and Stratix 10 GX and Arria 10 GX.- TSUGI
and also x5 over sampling Design Example for Agilex 7 F-Tile and Stratix 10 GX and Arria 10 GX.
