Occasional Contributorwhat's the main concern to set or not set associated clk and reset
In the component editor, it's required to fill the associated clk and reset.
As all the logic related to clk and reset already defined in the *.v design files, why should define once more here? Is there any issue if I leave it as none here?
Let me take SPI bus for example.
spi_miso is an input signal . It's not linked to any reset signal.
But spi_cs, spi_mosi, spi_clk can be reset by signal reset_n;
So should I put reset_n as associatedreset for overall SPI_BUS conduit? If yes, what's the impact on spi_miso?
The Component Editor knows nothing about the functionality of your custom component. As such, you have to specify the standard interface signal roles of your top-level ports (clock, reset, etc.) and the associated clock and reset for each standard interface (Avalon, AXI).
For the example you mention, it sounds like those signals are making up a conduit instead of a standard interface, confirmed by your screen capture. As such, associated clock and reset are not required for this type of interface. I think you may see warnings if you use the component in a system, but they're just warnings, not errors. You can set associated clock and reset since the Component Editor gives you the option, but I don't think it will cause any issues if you don't.
#iwork4intel
