Agilex7 F-TILE ethernet hard IP 200G

Now  we develop a project with agilex7 fpga.  In the project we generate 200Gx4 ethernet hard ip. 

during testing on-board,  the reset flow of the ethernet IP  failed to complete successfully:

The IP output signals o_rst_ack_n / o_tx_rst_ack_n / o_rx_rst_ack_n remain permanently High and never pull Low. This causes the input reset signals i_rst_n / i_tx_rst_n / i_rx_rst_n fed into the Ethernet IP to stay stuck in the Low-level reset state and never exit reset.

the following signal status as follow by read register:

tx_lanes_stable = 0

sys_pll_locked = 0

tx_pll_locked = 1

the IP reset sequence  in the  IP datasheet shows:

so what should we do for the next step? Do you have any suggestion?