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shvlad's avatar
shvlad
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6 years ago

What pins should be used for PCIe hard IP (on Arria 10)

I'm working with Arria 10 DEV KIT (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html) . I want to use FMC card to get additional PCIe. I've created a qsys system with HIP (Gen1, x1), arranged pins to met a mezzanine card requirements. 

set_location_assignment PIN_W8 -to pcie_refclk_100
set_location_assignment PIN_T5 -to rx_in0
set_location_assignment PIN_M1 -to tx_out0
 
set_instance_assignment -name IO_STANDARD HCSL -to pcie_refclk_100
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_in0
set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_out0

I've faced with error - Error (14530): tx_out0 is locked to a non-HIP location. The HIP locations are BB44 AF44 BB1 AF1.

I've looked at a lot of docs, for example https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf , https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01145_avmm-1_0.pdf

I've seen that I cant use some channels when GX nad TX combine and other constrains. But a don't anderstand why I can't use this pins.

Please help me to understend why the pins are restricted? Or what I do wrong and how I can fix it?

Best wishes, Vlad

5 Replies

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
    Icon for Contributor rankContributor
    6 years ago

    Hie,

    The pins are restricted because not all the transceiver channels are connected to the PCIe Hard IP(HIP). This information is available in Phy User Guide (refer to pg 11 onward on the FPGA architecture).

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf ,

    However for Arria 10 development kit, the PCIe channels are fixed as the HIP channels are connected to the board PCIe goldfinger. This is available in the Arria 10 development kit user guide: (refer to Table 6-16)

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10-fpga-prod-devkit.pdf.

    Hence, you can fix your error by referring to Pin Assignment in Table 6-16 of the Development Kit user guide.

    Please check if my explanation is sufficient for you to fix your issue. Do let me know if you have further questions.

    Regards,

    Nathan

    • shvlad's avatar
      shvlad
      Icon for New Contributor rankNew Contributor
      6 years ago

      Dear Nathan, thank you for your answer

      Unfortunately I can't to use your advice about using Table 6-16. I see that there are 4 hard PCIe controller on the chip and I want to use two of them or to use HIP near a FMC port to connect mezzanine card with root port connector.

      I've seen your first link, but I haven't seen restriction for bank 4F and 4C, therefore I can't understand what's happening.

      BR, Vlad

  • Nathan_R_Intel's avatar
    Nathan_R_Intel
    Icon for Contributor rankContributor
    6 years ago

    Hie Vlad,

    I found what is causing your issue. It related to logical channel placement.

    You are currently placing the transceiver channel on GXBR4D_CH5. Arria10 PCIe HIP usage is subjected to logical channel placement. Hence, the failure is related to logical channel placement; PCIe Gen1x1 requires the logical channel 0 to be placed in GXBR4C_CH4 instead of GXBR4D_CH5.

    This information is available in the Arria 10 PCIe AVMM ior AVST user guide.

    Ex: Refer to Figure 19:

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

    The device on the Arria 10 devkit has 72 transceiver channels and 4 HIP channels. Hence, there is one HIP located between bank 4C and 4D and the other located between 4E and 4F.

    This information is available in Arria10 Transceiver Phy User Guide – Figure 3:

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

    I have summarized the channel

    location and logical channel placement below:

    GXBR4D_CH5 -- pcie logical channel 7

    GXBR4D_CH4 -- pcie logical channel 6

    GXBR4D_CH3 -- pcie logical channel 5

    GXBR4D_CH2 -- pcie logical channel 4

    GXBR4D_CH1 -- pcie logical channel 3

    GXBR4D_CH0 -- pcie logical channel 2

    GXBR4C_CH5 -- pcie logical channel 1

    GXBR4C_CH4 -- pcie logical channel 0

    GXBR4F_CH5 -- pcie logical channel 7

    GXBR4F_CH4 -- pcie logical channel 6

    GXBR4F_CH3 -- pcie logical channel 5

    GXBR4F_CH2 -- pcie logical channel 4

    GXBR4F_CH1 -- pcie logical channel 3

    GXBR4F_CH0 -- pcie logical channel 2

    GXBR4E_CH5 -- pcie logical channel 1

    GXBR4E_CH4 -- pcie logical channel 0

    Hence, please make the changes proposed below and you should be able to place the required channels.

    Place PCIe Gen1x1 in either GXBR4C_CH4 or GXBR4E_CH4.

    Regards,

    Nathan

    • shvlad's avatar
      shvlad
      Icon for New Contributor rankNew Contributor
      6 years ago

      Dear Nathan,

      You answer is really full, you so help me! I've seen the pic but I could interpret the one. Thank you and all Intel FPGA support for you job!

      BR, Vlad