What pins should be used for PCIe hard IP (on Arria 10)

Hie Vlad,

I found what is causing your issue. It related to logical channel placement.

You are currently placing the transceiver channel on GXBR4D_CH5. Arria10 PCIe HIP usage is subjected to logical channel placement. Hence, the failure is related to logical channel placement; PCIe Gen1x1 requires the logical channel 0 to be placed in GXBR4C_CH4 instead of GXBR4D_CH5.

This information is available in the Arria 10 PCIe AVMM ior AVST user guide.

Ex: Refer to Figure 19:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

The device on the Arria 10 devkit has 72 transceiver channels and 4 HIP channels. Hence, there is one HIP located between bank 4C and 4D and the other located between 4E and 4F.

This information is available in Arria10 Transceiver Phy User Guide – Figure 3:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf

I have summarized the channel

location and logical channel placement below:

GXBR4D_CH5 -- pcie logical channel 7

GXBR4D_CH4 -- pcie logical channel 6

GXBR4D_CH3 -- pcie logical channel 5

GXBR4D_CH2 -- pcie logical channel 4

GXBR4D_CH1 -- pcie logical channel 3

GXBR4D_CH0 -- pcie logical channel 2

GXBR4C_CH5 -- pcie logical channel 1

GXBR4C_CH4 -- pcie logical channel 0

GXBR4F_CH5 -- pcie logical channel 7

GXBR4F_CH4 -- pcie logical channel 6

GXBR4F_CH3 -- pcie logical channel 5

GXBR4F_CH2 -- pcie logical channel 4

GXBR4F_CH1 -- pcie logical channel 3

GXBR4F_CH0 -- pcie logical channel 2

GXBR4E_CH5 -- pcie logical channel 1

GXBR4E_CH4 -- pcie logical channel 0

Hence, please make the changes proposed below and you should be able to place the required channels.

Place PCIe Gen1x1 in either GXBR4C_CH4 or GXBR4E_CH4.

Regards,

Nathan