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shvlad's avatar
shvlad
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6 years ago

What pins should be used for PCIe hard IP (on Arria 10)

I'm working with Arria 10 DEV KIT (https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html) . I want to use FMC card to get additional PCIe....
Nathan_R_Intel's avatar
Nathan_R_Intel
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6 years ago

Hie,

The pins are restricted because not all the transceiver channels are connected to the PCIe Hard IP(HIP). This information is available in Phy User Guide (refer to pg 11 onward on the FPGA architecture).

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/ug_arria10_xcvr_phy.pdf ,

However for Arria 10 development kit, the PCIe channels are fixed as the HIP channels are connected to the board PCIe goldfinger. This is available in the Arria 10 development kit user guide: (refer to Table 6-16)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10-fpga-prod-devkit.pdf.

Hence, you can fix your error by referring to Pin Assignment in Table 6-16 of the Development Kit user guide.

Please check if my explanation is sufficient for you to fix your issue. Do let me know if you have further questions.

Regards,

Nathan

shvlad's avatar
shvlad
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6 years ago

Dear Nathan, thank you for your answer

Unfortunately I can't to use your advice about using Table 6-16. I see that there are 4 hard PCIe controller on the chip and I want to use two of them or to use HIP near a FMC port to connect mezzanine card with root port connector.

I've seen your first link, but I haven't seen restriction for bank 4F and 4C, therefore I can't understand what's happening.

BR, Vlad