New ContributorI would like to know how DDR3 controller IP get configured in the FPGA with user provided timing parameters. The FPGA used is EP4SE230F29C2N. Provided the DDR3 interfaced with FPGA has a minimum tRFC of 160ns and user defined tRFC is 110ns, what is the actual timing generated/used by the IP?
Frequent ContributorHi the timing generated by the IP will follow what value that user set in the IP GUI. What is the value that you set in the GUI?
I am not aware why you said the FPGA has a minimum tRFC 160ns. Is this from a documentation?
New Contributor160ns is the minimum tRFC of DDR3 connected to FPGA. User defined tRFC to FPGA is 110ns, which actually violated the timing requirement.
I'm asking because I need to find out how critical it is for the difference between 160ns (DDR3) and 110ns (user defined timing). If the time generated by the IP has an extra buffer timing to accommodate the timing difference, then we might not need perform a image update of FPGA.
Frequent ContributorIf this case, the timing from FPGA will be 110ns (like what you set) with small variation due to device to device variation, but it will not varied from 110 to 160 with such big difference. So this seem like violated the DDR3 requirement.
However, I believe the DDR3 memory device will have some tolerance. I will suggest try to check is the original image still work correctly. If yes, I think you still can remain using original image.
New ContributorThanks for the suggestion. I'll try that.
Frequent ContributorTry to check across multiple boards. To ensure there is no marginal issue.
