What is the actual timing generated by FPGA IP vs user defined tRFC when interfaced with DDR3?

If this case, the timing from FPGA will be 110ns (like what you set) with small variation due to device to device variation, but it will not varied from 110 to 160 with such big difference. So this seem like violated the DDR3 requirement.

However, I believe the DDR3 memory device will have some tolerance. I will suggest try to check is the original image still work correctly. If yes, I think you still can remain using original image.