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AWong53's avatar
AWong53
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6 years ago

What is the actual timing generated by FPGA IP vs user defined tRFC when interfaced with DDR3?

I would like to know how DDR3 controller IP get configured in the FPGA with user provided timing parameters. The FPGA used is EP4SE230F29C2N. Provided the DDR3 interfaced with FPGA has a minimum tRFC...
BoonT_Intel's avatar
BoonT_Intel
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6 years ago

Hi the timing generated by the IP will follow what value that user set in the IP GUI. What is the value that you set in the GUI?

I am not aware why you said the FPGA has a minimum tRFC 160ns. Is this from a documentation?

  • AWong53's avatar
    AWong53
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    6 years ago

    160ns is the minimum tRFC of DDR3 connected to FPGA. User defined tRFC to FPGA is 110ns, which actually violated the timing requirement.

    I'm asking because I need to find out how critical it is for the difference between 160ns (DDR3) and 110ns (user defined timing). If the time generated by the IP has an extra buffer timing to accommodate the timing difference, then we might not need perform a image update of FPGA.