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AWong53's avatar
AWong53
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6 years ago

What is the actual timing generated by FPGA IP vs user defined tRFC when interfaced with DDR3?

I would like to know how DDR3 controller IP get configured in the FPGA with user provided timing parameters. The FPGA used is EP4SE230F29C2N. Provided the DDR3 interfaced with FPGA has a minimum tRFC...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

If this case, the timing from FPGA will be 110ns (like what you set) with small variation due to device to device variation, but it will not varied from 110 to 160 with such big difference. So this seem like violated the DDR3 requirement.

However, I believe the DDR3 memory device will have some tolerance. I will suggest try to check is the original image still work correctly. If yes, I think you still can remain using original image.

  • AWong53's avatar
    AWong53
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thanks for the suggestion. I'll try that.

    • BoonT_Intel's avatar
      BoonT_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      6 years ago

      Try to check across multiple boards. To ensure there is no marginal issue.