What does the APPS core in PCIe Example Design Do

Hello,

Yes, I had seen that. But I'm afraid it does not tell you how APPS works. Changing parameters in a "black box" APPS does not really help me to create my own system.

On page 17 it says APPS should have a altpcied_sv_hwtcl.v file associated with it, but I cannot find that anywhere in the install or online.

Thanks

Hello @Wincent_Altera ,

I'm prototyping a system that uses the PCIe Gen2 x1 interface on a Rasperry Pi Compute Module 4 connected to a Cyclone V SoC Eval board (I'm not using the HPS, just the fabric). The initial goal is to just have the PI see the FPGA PCIe endpoint. This would confirm the hardware is working and the PCIe IP in the FPGA is booting correctly (eg all resets). The equivalent of a PCIe "Hello World"

Then I would progressively add features to read/write data between the PI and FPGA.

I am of course reading the PCIe docs, but a useful example would be helpful. The docs you mention do not actually explain how the APPS core works. It's just a black box. So it does not help me write my own application. There are many signals APPS handles (resets, power, MSI .....) and it would be useful to have the source code for it.

A useful example would just create the PCIe Hard IP core, and transceiver reconfig core in Qsys, and export the signals a user app has to deal with to a top level design and provide HDL source code for how to handle all those signals.

Thanks

Hello @Wincent_Altera ,

I had been using those examples as well (eg the ep_gen1x4_22.1_balanced). They are somewhat helpful (no APPS or other black boxes in Qsys), and have a toplevel that shows how to connect to some of the QSYS outputs. It sort of shows how to handle resets. But the examples seem to be full of bugs, so I'm not sure how much I trust them. For example, the they do not meet timing and drive lines that are outputs. For example, reconfig_mgmt_readdata is an output from Qsys, but they drive it to zero. Many of the pins are assigned locations that do not exist (eg the pcie_rx and pcie_tx, pcie_refclk). The examples were clearly never actually run.

I ordered a Terasic board that seems to include useful examples. Includes Linux driver and application, and Quartus FPGA project (not just a .qsys file). There is a Qsys system, but no black boxes.Hopefully, it will help. The Linux driver is from Altera, but apparently from a Wiki that no longer exists.

I'll give a shot and hopefully get things working. You seem pretty knowledgeable about PCIe if I have more specific questions :-).

Thanks

Hello @Wincent_Altera

Unfortunately, we does not have much step by step example for all the pin assignments.

Because all of the application is quite different, user needs to define what they need to assign themself.

...

This was not just a generic example, it came with the Cyclone V Soc Development Kit CD. It seemed reasonable to assume it would actually work with the kit. That's the point of an example :-). It even included a .sof file (ep_gen1x4_22.1.sof). What board is that for if not the the one it came with?

But I'm quite familiar with Quartus and had no problem setting the pins correctly. But there were other issues such as the example driving ports that are outputs.

I've accepted the fact that useful examples are a lost art. It's not just Intel.

Thanks anyway.

@Wincent_Altera

Hopefully they will improve the examples. I don't have any further questions at the moment.

A useful example would show how to read and write to a buffer in user fabric either initiated by processor or FPGA.

I've checked many examples, including Arria 10 and Cyclone 10, and none show how the user FPGA code can do things such as:

1. Initiate a transfer from a buffer on the processor
2. Know when the processor has written data to a buffer on the FPGA
3. Send and interrupt from the FPGA to the processor

These are things all users, regardless of application, would need to know. They all have the same black APPS.

Thanks