What does the APPS core in PCIe Example Design Do

Hello @Wincent_Altera ,

I'm prototyping a system that uses the PCIe Gen2 x1 interface on a Rasperry Pi Compute Module 4 connected to a Cyclone V SoC Eval board (I'm not using the HPS, just the fabric). The initial goal is to just have the PI see the FPGA PCIe endpoint. This would confirm the hardware is working and the PCIe IP in the FPGA is booting correctly (eg all resets). The equivalent of a PCIe "Hello World"

Then I would progressively add features to read/write data between the PI and FPGA.

I am of course reading the PCIe docs, but a useful example would be helpful. The docs you mention do not actually explain how the APPS core works. It's just a black box. So it does not help me write my own application. There are many signals APPS handles (resets, power, MSI .....) and it would be useful to have the source code for it.

A useful example would just create the PCIe Hard IP core, and transceiver reconfig core in Qsys, and export the signals a user app has to deal with to a top level design and provide HDL source code for how to handle all those signals.

Thanks