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corestar's avatar
corestar
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2 years ago

What does the APPS core in PCIe Example Design Do

This is my first attempt at using PCIe in a Cyclone V using Quartus 19.1 Lite. I'm using the Cyclone V SoC Development kit. I loaded the example design: hip_cv_x1_g1_ast64_140.qar to attempt t...
Pcie
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Thanks for your feedback, What the best I can help at the moment is to submit an internal ticket to related team.

Hope they will work on include useful examples. Includes Linux driver and application and some of the example connection for the APPS core.


Do you still have any further question that I can help you more ?


Regards,

Wincent_Intel


corestar's avatar
corestar
Icon for Contributor rankContributor
2 years ago

@Wincent_Altera

Hopefully they will improve the examples. I don't have any further questions at the moment.

A useful example would show how to read and write to a buffer in user fabric either initiated by processor or FPGA.

I've checked many examples, including Arria 10 and Cyclone 10, and none show how the user FPGA code can do things such as:

  1. Initiate a transfer from a buffer on the processor
  2. Know when the processor has written data to a buffer on the FPGA
  3. Send and interrupt from the FPGA to the processor

These are things all users, regardless of application, would need to know. They all have the same black APPS.

Thanks

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,

    Unfortunately, Cyclone V consider a legacy device.
    Hence the example might not be as complete as other new devices.

    If you need to develop something for business use, I would recommend you to look at our latest product
    https://www.intel.com/content/www/us/en/products/details/fpga/agilex.html
    You may contact Intel distributor in your region if you would like to know more
    https://www.intel.com/content/www/us/en/partner/showcase/partner-directory/distributor.html#sort=relevancy

    Please accept my apology for cannot help much regarding your queries.
    Regards,
    Wincent_Intel

    • corestar's avatar
      corestar
      Icon for Contributor rankContributor
      2 years ago

      Hello @Wincent_Altera

      I'm afraid a $40,000 Agilex chip will not work for our application :-). Our Arrow rep assured us the Cyclone V would not EOL before 2032. I assume that is still valid? The Arria 10 is a possibility, but the prices of those has doubled as well.

      I'll figure it out. I have the Linux side working with a PCIe driver (which I had assumed would be the hard part) for a simple PCIe RS-232 card. So with enough effort, I'll figure out the FPGA side.

      Thanks

      Begin irrelevant side notes:

      One thing I wondered about is why in the world they did not simply integrate the XVR Reconfig Controller and its driver into the PCIe Hard IP core. Made no sense. Looking at the Arria 10, they appear to have done exactly that.

      Not your fault they don't have useful examples or appear to even understand the concept of a useful example. It's odd since the Altera online training was always superb and Quartus is vastly superior to Xilinx (which I used for many years) and Vivado. But the PCIe training was not useful.

      I first moved to Altera from Xilinx because their JESD204b core was incomprehensible, but without ever having used Quartus, got it running in a few days with Altera tools. Same with Ethernet and many other projects. But for some reason, they decided to make PCIe difficult.

      End of irrelevant side notes: