Forum Discussion
corestar
Contributor
ContributorWhat does the APPS core in PCIe Example Design Do
This is my first attempt at using PCIe in a Cyclone V using Quartus 19.1 Lite. I'm using the Cyclone V SoC Development kit. I loaded the example design: hip_cv_x1_g1_ast64_140.qar to attempt t...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
For further information about APPS you can refer document below
https://cdrdv2-public.intel.com/655090/ug-01110-1_5.pdf
at page 25/288 it mention how this root port BFM configures the DUT.
Regards,
Wincent_intel
corestarContributor
ContributorHello,
Yes, I had seen that. But I'm afraid it does not tell you how APPS works. Changing parameters in a "black box" APPS does not really help me to create my own system.
On page 17 it says APPS should have a altpcied_sv_hwtcl.v file associated with it, but I cannot find that anywhere in the install or online.
Thanks
