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corestar's avatar
corestar
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2 years ago

What does the APPS core in PCIe Example Design Do

This is my first attempt at using PCIe in a Cyclone V using Quartus 19.1 Lite. I'm using the Cyclone V SoC Development kit. I loaded the example design: hip_cv_x1_g1_ast64_140.qar to attempt t...
Pcie
  • corestar's avatar
    corestar
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    2 years ago

    Hello @Wincent_Altera ,

    I had been using those examples as well (eg the ep_gen1x4_22.1_balanced). They are somewhat helpful (no APPS or other black boxes in Qsys), and have a toplevel that shows how to connect to some of the QSYS outputs. It sort of shows how to handle resets. But the examples seem to be full of bugs, so I'm not sure how much I trust them. For example, the they do not meet timing and drive lines that are outputs. For example, reconfig_mgmt_readdata is an output from Qsys, but they drive it to zero. Many of the pins are assigned locations that do not exist (eg the pcie_rx and pcie_tx, pcie_refclk). The examples were clearly never actually run.

    I ordered a Terasic board that seems to include useful examples. Includes Linux driver and application, and Quartus FPGA project (not just a .qsys file). There is a Qsys system, but no black boxes.Hopefully, it will help. The Linux driver is from Altera, but apparently from a Wiki that no longer exists.

    I'll give a shot and hopefully get things working. You seem pretty knowledgeable about PCIe if I have more specific questions :-).

    Thanks