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Altera_Forum
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11 years ago

VIP Scaler II Megacore: Garbage at bottom of image

Hi,

I'm trying to upscale a 1024x768 image to 1280x1024 using the Altera VIP Scaler II IP Core.

I have set up the Clocked Video Input IP core to receive the image signal, then the image is upscaled by the VIP Scaler II IP Core and finally converted back using the Clocked Video Output IP core.

Using nearest neighbor algorithm this works great, the image is beeing displayed completely on the connected TFT display.

But when I change to a better algorithm like bilinear or polyphase interpolation, approximately 5 lines at the bottom of the screen show garbage and the unterflow signal goes high. All other pixels are beeing displays correctly.

I have tried all kinds of different settings in all 3 IP cores like changing FIFO depth to the maximum possible, but there is absolutely no change in the output image.

It looks like the scaling algorithm is waiting for more data at the end of the image frame to finish the upscaling process and therefore the fifo in the Video Output IP core is running empty, repeating the last available pixel for the rest of the image.

Sine I do not have any external memory connected, I can't add a frambuffer. But I don't think this is the actual problem, because changing the fifo settings does not change anything.

Does anybody have other suggestions of what might be the problem and how to solve it?

I have attached screenshots of the VIP Scaler II and Clocked Video Output IP core settings. Probably I did miss something simple.

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  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Since I do not have any memory connected to the FPGA, I can not use a framebuffer. Instead I have replaced the CVI with the Test Pattern Generator. This should be similar to the framebuffer since it can deliver data whenever requestet.

    Now the image is displayed correctly and the underflow signal stays inactive, as expected.

    The next thing I have tried was replacing CVI and CVO with CVI II and CVO II. But since those are limited to 4k FIFO depth the problems in the output image start around line 25 instead of 1019.

    So I went back to CVI but kept using CVO II. Now it looks same as before but after a couple of minutes the image changed from false data in the last 5 lines to false data in the last ~1015 lines.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    bktemp - Good idea to plug in the test pattern generator and verify that the pipeline functions correctly without the CVI. Based on everything you've described here I am stumped as to what the problem is. If you figure is out please post back here and let us know.

    Good luck!
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You mean the main clock for CVI/CVO not the pixelclock? All 3 main clocks are connected together and run at 150MHz. The input pixel clock is 60MHz, the output pixel clock is 100MHz.