Altera_Forum
Honored Contributor
12 years agoVIP fmax for Cyclone IV device
Hi,
I have a question about the VIP fmax for CycloneIV FPGA. The chapter 1 in VIP user guide has a fmax table with regard to each IP. For example, the clocked video input IP has a fmax of 116.36MHz when converting a 1080p60 SDI video to avalon-st package on EP4CGX15BF14C6. Is this fmax fast enough to handle 1080p60 video? To my understanding, 1080p60 video is sent with a pixel clock of 148.5MHz and I think a minimal fmax should be at least 148.5MHz in order to correctly convert video to avalon-st packet. Therefore, if I'm going to do some video processing for 1080p60 video, I may need to use other FPGA device family such as Arria. Is my thinking correct? Thanks.