Altera_Forum
Honored Contributor
13 years agoUART IP Core Interrupt
Hi,
I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). I have read the spec on the Core and the Bus. I need a basic Rx Interrupt Flag. This is the RRDY flag set by the IRRDY Bit. The problem is the RRDY flag is constantly set to 1. I read the data from the rxdata register, which is supposed to clear the flag, but the flag remains high. Do you have any idea how to clear this flag? or properly read the register? I am currently reading the register by setting the address to 0x0000 (the rxdata register), select Read = 1 and write = 0. and waiting 2 clock cycles. The data read from the rxdata is the data i sent from my computer through an FTDI RS232 Chip. Any ideas? Thanks, Tom