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Altera_Forum
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12 years ago

UART IP Core Interrupt

Hi, I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). I have read the spec on the Core and the Bus. I need a basic Rx...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you for the response, but it did not work.

I disabled the IRRDY, and read the status bit, and the RRDY flag is a constant 1.

I enabled the IRRDY, and wrote the status bit to 0, and the RRDY flag is a constant 1.

Any other ideas?