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Altera_Forum
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12 years ago

UART IP Core Interrupt

Hi, I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). I have read the spec on the Core and the Bus. I need a basic Rx...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The data ia always correct, but I can read the same rx value multiple times.

I think the problem might be with the readyforread and the dataavailable pins because I dont know where they connrct in the avalon mm