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Honored Contributor
Honored ContributorUART IP Core Interrupt
Hi, I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). I have read the spec on the Core and the Bus. I need a basic Rx...
Altera_ForumHonored Contributor
Honored ContributorAFAIK if you don't use interrupts (i.e. you don't set IRRDY bit in control register) RRDY status bit indeed behaves that way and it is automatically cleared when you read the rx data.
If irq is enabled through IIRRDY bit, you must explicitly acknowledge the irq by writing 0 to the status register, otherwise the flag remains asserted.
