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Honored Contributor
Honored ContributorUART IP Core Interrupt
Hi, I am designing a VHDL Avalon Master Module, which is connecting through Qsys to the UART IP Core (address 0x0000 to 0x001f). I have read the spec on the Core and the Bus. I need a basic Rx...
Altera_ForumHonored Contributor
Honored ContributorThen you probably have a timing problem in the core itself or with the Avalon interface.
Does the data you read from the rx register always match the real rx data?
