Altera_Forum
Honored Contributor
13 years agoTwo sustom avl mm master to ddr3 uniphy controller
First I have created a custom avl mm master to DDR3 Uniphy controller slave, connected it to DDR3 controller along with pll in QSYS and using that I have perform Write read operations in the DDR3 memory module (MT41J128M16HA).
Now I created a second master for the same slave which will only read from DDR3 memory module and connected in the QSYS. The system was generated and compiled. After that I found the avl_waitrequest of the ddr3_controller is not going low ie 1'b0 after the initialization and calibration of memory module. So the Questions are 1) Can I connect two custom masters of DDR3 Uniphy controller memory mapped slave? 2) If Yes then where I am going wrong ? since avl_waitrequest is not going low and I can not perform write or read operations from memory? 3) Is there any specific way so that I can connect two master to one avl_mm_slave like using some kind of multiplexer or like that? 4) Why my two master one slave system is not working ?