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Honored Contributor
Honored ContributorTwo sustom avl mm master to ddr3 uniphy controller
First I have created a custom avl mm master to DDR3 Uniphy controller slave, connected it to DDR3 controller along with pll in QSYS and using that I have perform Write read operations in the DDR3 mem...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- waitrequest is only valid when an operation is going on, so you shouldn't read it before doing a read or write operation. Did you try to perform a read or write operation anyway? --- Quote End --- I checked waitrequest == 1'b0 before writing the first data into the memory and then keep checking it before any read or write. This method I have used when single master is connected to ddr3 controller and it worked well. I was able to write into memory then I read the written data modified it and written it back into the memory. Now I want to read this modified data with second master (This master will only read it wont write anything into memory). Can I do it?
